Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
In multi-core processor architectures, multiple processor cores may be included in a single integrated circuit die or on multiple integrated circuit dies that are arranged in a single chip package. A cache may be used to store data for access by one or more of the processor cores. The data can be a subset of data stored in a larger memory that is typically located outside of the die. Each processor core may be provided with a cache that is used to store data for the corresponding processor. As a single piece of data may be stored in multiple caches, a cache coherence protocol may be employed to keep track of the data stored in multiple caches. State information for data blocks in the cache may be stored in a directory and a cache coherence protocol may be implemented to ensure that the appropriate data is identified and returned in response to requests for data blocks.